Sun Sep 12 23:00:31 EDT 1999  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1b2 to 1b3.

1999-09-08  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-tag): Conditionalize reset block with
	`ifdef exemplar if NO-RTL-SIMULATION flag is present.

	* simsynch.scm(synch:declare): Uses current *block*, instead of
	confounding blocks and ptags.

1999-09-07  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (call-with-classified-pins): Added output-enable to
	outputs when simple symbol.

1999-09-03  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (generate-inc-file): Conditionalized on feature
	'lift-bus.

	* simsynch.scm (call-with-classified-pins): Conditionalized on
	feature 'lift-bus.

Fri Sep 3 18:33:22 EDT 1999  Aubrey Jaffer  <jaffer@scm.colorage.net>

	* Makefile (VERSION): Bumped from 1b1 to 1b2.

1999-09-03  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (generate-inc-file): Raise bidirectional signals to
	include file for top-level.

	* simsynch.scm (call-with-classified-pins): simplified
	input/output section.
	(call-with-classified-pins): Output inputs and outpus for
	bidirectional signals.

	* scm2vrlg.scm (translate-exp): Treat EQV? like =.

1999-09-02  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* models.scm (make-ram-array make-ram): Fill RAM with prototype.

1999-09-01  Radey Shouman  <Radey_Shouman@splashtech.com>

	* logic.scm (read:sharp): Now skips leading semi colons in #;
	lines.

1999-09-01  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* synch.texi (Infrastructure): Added documentation of #; and
	comment.

1999-08-31  Radey Shouman  <Radey_Shouman@splashtech.com>

	* logic.scm: Added #; read syntax for (comment ...) forms.

1999-08-31  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* models.scm (synch:fifo): Added COMMENTs to generated code.

1999-08-30  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (outcomment): fixed comment indentation.

1999-08-30  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (generate-module-header): Now looks up comments in
	signal-table.

	* scm2vrlg.scm (out-decl): Will emit comments in declarations.

1999-08-29  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (out-decl): Added comments argument.

	* logic.scm (comment): Added.

	* simsynch.scm (create-board): Added optional-documentation
	strings for ptag, block, constants, and signals.

	* logic.scm (comment): Added.

1999-08-28  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): Added support for *xxxx*.

	* simsynch.scm (*xxxx*): Leave initial-state unspecified.

1999-08-24  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (synch:define-signal): Now checks whether
	INITIAL-STATE argument is a list with car SYNCHRONOUS, if so,
	synchronous reset Verilog will be generated for the defined
	signal.

1999-08-23  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-tag): Now checks block-table
	SYNCHRONOUS-RESET? flag.
	*simsynch (create-board): (synch:register-block):
	Added CLOCK-FREQUENCY, SYNCHRONOUS-RESET? fields to BLOCK table.

1999-08-17  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2mach.scm (translate1): Checks for unrecognized flags.
	* scm2vrlg.scm (translate1): Now checks for recognized flags.
	* simsynch.scm (synch:check-flags): Added to generate warnings
	about unrecognized flags.

	* scm2vrlg.scm (translate-tag): Recognizes SYNCHRONOUS-RESET flag,
	to remove reset signal from Verilog sensitivity list.

	* simsynch.scm (create-board): Added FLAGS table for translation
	target dependent (per signal) flags.
	(synch:signal-flags): Retrieves flags list.
	(synch:add-signal-flag): Adds flag to table.
	(synch:declare): Macro interface to SYNCH:ADD-SIGNAL-FLAG.

1999-07-30  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): moved check from "simsynch.scm".

	* simsynch.scm (synch:define-signal): moved check to
	"scm2vrlg.scm".

Fri Jul 30 12:11:05 EDT 1999  Aubrey Jaffer  <jaffer@scm.colorage.net>

	* Makefile (VERSION): Bumped from 1b0 to 1b1.

1999-07-30  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (synch:define-signal): check that vectorized
	signals have numeric initial values and vice-versa.

1999-07-29  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (synch:print): Removed call to dma:dword-read-count.

1999-07-27  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): Don't vectorize LOGBIT? unless
	first argument is number.
	(translate-case): was incorrect for logical expressions lacking
	'(else #f).

1999-07-23  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-assignment): Take POLarity into account
	when eliding assignments.

1999-07-22  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): prettied BOOLEANS-TO-NUMBER
	expansion indentation.

1999-07-22  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-exp): Added support for
	BOOLEANS-TO-NUMBER, translates to Verilog concatenation eg {foo,
	bar, baz} .

1999-07-14  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): Fixed translation of LOGTEST.

1999-07-13  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): bool? argument was not being
	correctly set -- fixed.
	(translate-case): added.  Only boolean case statements can be
	translated to verilog || and &&.

1999-07-01  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* synch.texi (Translation): Expanded.

	* logical.v: Gave widths to all identifiers.

1999-06-22  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* models.scm (synch:fifo): Changed ".." to ":".

1999-06-17  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): Translate modulo -> logand (not %).

	* logical.v: Added random_Percent.

1999-06-13  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-case-clause): Suppress self-set defaults.
	(translate-assignment): Suppress self-sets.
	(out-decl): Fixed array declaration.

1999-06-11  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): Added LOGTEST.

1999-06-09  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* models.scm (synch:fifo): Added checks for reading from empty and
	writing to full.

1999-06-09  Radey Shouman  <Radey_Shouman@splashtech.com>

	* edf2vrlg.scm: Added, edif netlist to verilog translator.

1999-05-25  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-exp): Fixed output of negative constants.

1999-05-25  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-power-connections): Attempts to print
	power and ground connections in Verilog format.

	(translate-netlist): Prints declarations, instantiations of u-numbered
	parts, and power connections, as Verilog.

1999-05-25  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (number-lines?):. (vprintf): added.
	(out): (generate-verilog-header): Fixed line numbers.

1999-05-25  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (db:register-u-ptag): Added, now called by
	DB:READ-U-PTAG .

	(db:read-net): Now creates ptags and u-ptags for unrecognized
	u-numbers read from netlist.

	* simsynch.scm (db:read-net): Now reads non-integer pin names from
	netlist.

1999-05-24  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-exp): Output numbers in base 2.

1999-05-24  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-netlist): Added, outputs Verilog version
	of netlist.

	* scm2vrlg.scm (translate-tag): Fixed "wire" declarations for
	macro signals.

	* scm2vrlg.scm (translate-tag): Split output into one file per
	module.
	(call-with-verilog-output): Fluid lets verilog output port.

1999-05-23  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (byte0 byte1 byte2 byte3): Added functions for wide
	numbers in synch:print.

1999-05-17  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-<>): added inequalities.  But doesn't <=
	mean assignment?

1999-05-13  Radey Shouman  <Radey_Shouman@splashtech.com>

	* pins.scm (pins->dcm): Now writes section of .acf file as well as
	.dcm file.

	* drawpins.scm (flush-ws): Fixed to really flush whitespace.

	(read-coord-strings-3): (read-coord-strings-4): Now named for
	number of fields they read, were *both* named read-coord-strings.

	* scm2vrlg.scm (write-acf-file): Added, writes a section of the
	.acf file specifying pin assignments.

	* run.scm (simsynch-vicinity): Now defined as top-level procedure.

1999-04-29  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* logic.scm (ptag-stripped):
	(ptag-prefix): don't mistake [31:0] for a PTAG.

	* simsynch.scm (create-board): Removed PLD table.  Just use string
	supplied to synch:register-ptag.
	(synch:definput):
	(synch:defreginput):
	(synch:define): only strip signal-name if it has the ptag.

1999-04-01  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* pins.scm (type->dir): Added GCLK type.

1999-03-23  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-name): Eliminated first, full name
	argument.

	* simsynch.scm (create-board): Replaced BASENAME table with
	PIN-BASENAME table, mapping basenames to entries in the PIN table.

	(create-board): Added BASENAME table, for scm2vrlg
	conversion: given name stripped of bounds, find signals with
	bounds & unique defining ptag.

1999-03-22  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (define-synchronous-system): Reset state
	initialized earlier.

1999-03-22  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-tag): Changed condition for "always @
	(posedge <clock>" from name==initial-state to name==reset.

	* simsynch.scm
	* run.scm (print-netlist-connections): Now takes design, netlist
	file, and u-number->ptag mapping file as arguments.  No longer
	prints out nets not driven by any signals in the database.  Moved
	to run.scm.

1999-03-19  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (db:netlist-connects net-name bounds): Added,
		returns list of ((ptag signal-name) ...) connected to a
		net-name read from a netlist file.
	(print-netlist-connections):  Added.
	Added NAME field to the pindex table, a symbol eq? to the
	original signal-name provided to synch:define-pin.

1999-03-11  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-name): Names of pin signals now
	UPPERCASED.  Others have ptag prefixed.  Inverted signals have _n
	suffix.

1999-02-23  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (create-board): Split NETLIST-AGGREGATE table into
	NETLIST-AGGREGATE and NETLIST-NON-AGGREGATE, since there are
	aggregate nets with the same names as non-aggregate nets.

	(db:print-power-connections): Prints first aggregate nets, then
	non-aggregate.

	* simsynch.scm (create-board): Added table NETLIST-AGGREGATE which
	contains the names of each net name with trailing index deleted.

	(db:read-net): Now parses trailing digits as an index, the NETLIST
	table now uses name and index as primary keys.  -1 as index means
	no trailing digits.

	(db:print-power-connections):  Prints aggregate nets together.

1999-02-12  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (db:print-power-connections): Added, walks netlist
	printing nets connected to power or ground nets by resistors.

	(db:read-net) Added field R-PINS to netlist table
	for resistors in a net.  Added table RESISTOR-NETS to map
	resistors to nets they connect.

1999-02-11  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (db:read-net): Added sheet number to netlist table.

1999-02-10  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (db:read-u-ptag): Now registers unique ptags as
	necessary.

1999-02-05  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (define-tables): Renamed SIGNAL-NET table to
	NETLIST, added NETLIST-INVERSE table.

	(db:read-net): Now also inserts rows in netlist-inverse table.

	* simsynch.scm (bus-expression): Added, returns expression
	combining several vectorized signals.

	(process-aggregate-pins): Stub added.

	* scm2vrlg.scm (get-bounds): (merge-bounds):
	(call-with-classified-pins): Moved to simsynch.scm, are not
	dependant on translation target.

	* simsynch.scm (create-board): Added tables: U-PTAG, for
	tranlating u-numbers from netlist to ptags, SIGNAL-NET for
	mapping signal names to pin numbers.

	(db:read-u-ptag): Added, reads Scheme list associating
	u-numbers to ptags, eg cz-umap.scm.

        (db:read-net): Added, reads netlist.

1999-02-04  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (db:read-pins): Now reads BGA pin files.

	* drawpins.scm (flush-ws): Added to allow Scheme style comments
	with leading whitespace in .pin files.

1999-02-02  Radey Shouman  <radey@bobo.colorage.net>

	* drawpins.scm (draw-pins): Added thicker lines, lines slightly
	offset, row and column labels.

1999-01-27  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-exp):
	(translate-and):
	(infix-translate-exp):
	(optionally-parenthesize): Added BOOL? argument so test
	expressions are translated into && and ||.

1999-01-27  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (instantiate): Removed redundant (last) argument.

1999-01-20  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (instantiate): added argument HEADER? so
	instantiations are explicit form.

1999-01-17  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* ANNOUNCE: added.

Sun Jan 17 11:24:43 EST 1999  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1a3 to 1b0.

1999-01-13  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-and): added.  Turn (and a ... z) into
	(if (&& a ...) z 0).

1999-01-12  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* Makefile (version.txi): support added.

	* synch.texi (SIMSYNCH_VERSION): abstracted to version.txi.

1999-01-08  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): translate booleans as 0 and 1.

	* simsynch.scm (create-board): removed constants `f' and `t'.

	* scm2vrlg.scm (negate-result?): removed; instead pass polarity
	argument to translate-assignment.

1998-12-16  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (instantiate): Added comma output where necessary.

1998-12-15  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* simsynch.scm (dump:spew): dump stuff simplified.

1998-12-15  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (synch:dump-vector): (synch:dump-scalar): Added
	functions for writing Verilog compatible dump files.

1998-12-15  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (instantiate): Now takes separate signal group
	argument; print nice comments.
	(generate-module-header): Now pretty-prints scheme code for
	dumping module state.
	(merge-bounds): Now keeps track of pin names associated with
	merged signal.

1998-12-14  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (call-with-classified-pins): only imports/exports
	pins and signals used by other blocks.

	* simsynch.scm (used-in-table mark-uses used-by-other-blocks?):
	Created to keep track of which signals are used in which blocks.

1998-12-11  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): include "logical.v" from each
	non-trivial module.
	(call-with-classified-pins): classify internal signals as
	input and output if within block.
	(translate-tag): create declarations of macros (wire) before
	assign statements.

1998-12-10  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-tag): Now generates separate modules for
	each block within a ptag.
	(translate-text-macros): removed; macros now generate assign =
	statements.
	(out-bufs out-buf): removed (already commented out).
	(generate-module-header): don't generate constants for trivial modules.
	(instantiate): used for both `module' statements and instantiations.

1998-11-10  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): shift direction was backwards.

1998-11-09  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): self-setting signals reset
	removed.

	* scm2vrlg.scm (translate-tag): outputs conditional assignments
	(with ..'bz) rather than bufif1 statements.

	* scm2vrlg.scm (translate-assignment): Restored self sets.  =
	changed to <= for assignments.

1998-10-07  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): fixed self-initing/input register
	reset generation.

Sat Aug 8 22:57:38 EDT 1998  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1a2 to 1a3.

1998-07-21  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (ptag-stripped): return #f for 'tag: argument.
	(ptag-stripped): return number if stripped pin-name is.

	* simsynch.scm: pin-number and pin-num renamed to pin-name and
	pin-nam.  PTAG can now be specified on pin-nam.  Pin-nams can be
	vectorized (dq[32..00]).

	* logic.scm (ptag-stripped):
	(ptag-prefix): now pass numbers.

	* simsynch.scm (synch:define): now takes optional NEXT-FUNCTION
	argument.

1998-07-20  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm (translate-assignment): elides self-sets.

	* models.scm (synch:fifo): no longer generates external names.
	All are passed as arguments.
	* logic.scm (array-bounds): puts out nicer looking index
	calculations.

1998-07-17  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (symbol-append): beefed up to tolerate strings and numbers.

	* scm2vrlg.scm: Added array support.

	* models.scm (synch:fifo): added macro to instatiate FIFO memory.

1998-07-17  Aubrey Jaffer  <jaffer@colorage.com>

	* simsynch.scm (signal-table:get-init-fun): added.

	* logic.scm (array-bounds): added.

	* scm2vrlg.scm (translate-tag): moved call to
	translate-text-macros before generate-module-header.
	(call-with-classified-pins): now knows about arrays.

1998-07-16  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm (translate-exp): ash of negative numbers now uses
	`>>'.

	* synch.texi (Models): Added chapter.

	* simsynch.scm (pld): added ORCA3 package types.
	(synch:define-bus): Doesn't count #t enabled drivers -- these are used
	to model pullup/down.

	* scm2vrlg.scm (translate-exp): added `+' and `-'.

	* models.scm (make-ram-array): added.

1998-07-15  Aubrey Jaffer  <jaffer@colorage.com>

	* models.scm (make-ram): added.

1998-06-11  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (booleans-to-number): commented out warning.

	* simsynch.scm: Added CHECK-TURNAROUND feature.  This enables
	checks generated by synch:define-bus.

1998-06-08  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm (out-decl merge-bounds call-with-classified-pins):
	split out from generate-verilog-header.
	(generate-stimulus): now instantiates module with symbols.  primitive
	initial assignments added.

1998-05-29  Aubrey Jaffer  <jaffer@colorage.com>

	* Makefile (expander.scm): removed.

	* simsynch.scm (synch:set!): multiple synch:set!s now COMPOSE-SETS
	of new-states.

	* models.scm (make-fifo): added optional width-prototype field.

1998-05-26  Radey Shouman  <radey@colorage.com>

	* run.scm: Added error message for unknown translate target.

	* scm2vrlg.scm: Added support for BITWISE-IF.

1998-05-26  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm, scm2mach.scm: Added BIT-FIELD as alias for BIT-EXTRACT.

	* Makefile: split html target into html and cvshtml.

	* synch.texi: Included and reordered documentation for new
	(SLIB/SCM) logical operations.

	* simsynch.scm (define-synchronous-system): fixed
	(<block-name> <signal>) to work during reset.

1998-05-22  Aubrey Jaffer  <jaffer@colorage.com>

	* simsynch.scm, scm2vrlg.scm, scm2mach.scm:
	(<block-name> <signal>) now retrieves value.

	* scm2vrlg.scm, simsynch.scm, scm2mach.scm:
	SYNCH:PRE no longer requires (nor works with) #.

	* Makefile: models was missing from distribution.

1998-05-21  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm: Includes "models.scm".

1998-05-20  Aubrey Jaffer  <jaffer@colorage.com>

	* models.scm: changed make-uniform-array prototype to #xffffffff.

Thu May 21 22:03:34 EDT 1998  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1a1 to 1a2.

1998-05-20  Aubrey Jaffer  <jaffer@colorage.com>

	* models.scm: changed make-uniform-array prototype to #xffffffff.

1998-05-19  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm: fixed compose-sets

	* models.scm: fifo:clear added.

	* scm2vrlg.scm: Made NOT ifable.

	* scm2vrlg.scm: Added case-eval; no longer substitute values for
	constants in CASE statements.

	* scm2mach.scm: case-eval: no longer need to substitute values for
	constants in CASE statements.

	* scm2mach.scm: MACHXL string constant number must not have
	enclosing parentheses.

1998-05-14  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm: In symbol names : => _

	* simsynch.scm, scm2vrlg.scm, scm2mach.scm: Translators now handle
	defconst (and , in casev).

1998-05-13  Aubrey Jaffer  <jaffer@colorage.com>

	* simsynch.scm: CEVAL added; evals constant

	* scm2vrlg.scm: translate-= replaced using verilog ==

	* scm2mach.scm: Added CASEV support.

1998-05-12  Aubrey Jaffer  <jaffer@colorage.com>

	* synch.texi, scm2vrlg.scm, logic.scm: defconst definition made
	conditional; (scm now defines).  memocase -> casev

	* logic.scm, ChangeLog: logic.scm (memocase): Now case compatible
	with unquote or unquote-splicing in datum-list.

	* .cvsignore: added core

	* Makefile: A dummy directory (like core/) needs to be in the
	source dir in order to get a pane with the sequential log button
	in it. (cvs2html)

1998-05-12  radey  <radey@scm.colorage.net>

	* synch.texi: documentation for memocase

1998-05-12  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (memocase): Now case compatible with unquote or
	unquote-splicing in datum-list.

Thu Oct 30 10:38:54 1997  Aubrey Jaffer  <jaffer@martigny.ai.mit.edu>

	* logic.scm (count): count booleans added.

Wed Jun 11 16:01:27 1997  Aubrey Jaffer  <jaffer@martigny.ai.mit.edu>

	* simsynch.scm (define-synchronous-system): now keeps track of
	SYNCH:STATE explicitly.

Fri May 16 10:08:30 1997  Aubrey Jaffer  <jaffer@martigny.ai.mit.edu>

	* scm2mach.scm (compile-tops): headers now use coded time in time
	field.  CZ support added; slightly different format.

Thu Apr  3 17:17:11 1997  Aubrey Jaffer  <jaffer@martigny.ai.mit.edu>

	* run.scm (translate): generalized for use with DESIGN.
