!@(#)RELEASE VERSION Sun Patch 113820-02 2003/11/19
!
! @(#)libm.m4 1.22 03/11/05 SMI
!
! Copyright 11/05/03 Sun Microsystems, Inc.  All Rights Reserved.
!
	.inline	sqrtf,1
	fsqrts	%f1,%f0
	.end

	.inline	sqrt,1
	fsqrtd	%f0,%f0
	.end

	.inline	ceil,1
	fzero	%f4
	fnegd	%f4,%f8
	fabsd	%f0,%f6
	sethi	%hi(0x43300000),%o2
	sllx	%o2,32,%o2
	stx	%o2,[%sp+0x87f]
	ldd	[%sp+0x87f],%f2
	fcmpd	%fcc0,%f6,%f2
	fmovduge %fcc0,%f4,%f2
	fand	%f0,%f8,%f8
	for	%f2,%f8,%f2
	siam	6
	faddd	%f0,%f2,%f0
	siam	4
	fsubd	%f0,%f2,%f0
	siam	0
	for	%f0,%f8,%f0
	.end

	.inline	floor,1
	fzero	%f4
	fnegd	%f4,%f8
	fabsd	%f0,%f6
	sethi	%hi(0x43300000),%o2
	sllx	%o2,32,%o2
	stx	%o2,[%sp+0x87f]
	ldd	[%sp+0x87f],%f2
	fcmpd	%fcc0,%f6,%f2
	fmovduge %fcc0,%f4,%f2
	fand	%f0,%f8,%f8
	for	%f2,%f8,%f2
	siam	7
	faddd	%f0,%f2,%f0
	siam	4
	fsubd	%f0,%f2,%f0
	siam	0
	for	%f0,%f8,%f0
	.end

	.inline	ilogb,1
	st	%f0,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	sethi	%hi(0x7ff00000),%o1
	andcc	%o0,%o1,%o0
	bne,pt	%icc,2f
	nop
	sethi	%hi(0x43500000),%o0
	sllx	%o0,32,%o0
	stx	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f2
	fmuld	%f0,%f2,%f0
	st	%f0,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	andcc	%o0,%o1,%o0
	bne,pt	%icc,1f
	nop
	sethi	%hi(0x80000001),%o0
	or	%o0,%lo(0x80000001),%o0
	ba	4f
	nop
1:
	srl	%o0,20,%o0
	sub	%o0,0x435,%o0
	ba	4f
	nop
2:
	subcc	%o1,%o0,%g0
	bne,pt	%icc,3f
	nop
	sethi	%hi(0x7fffffff),%o0
	or	%o0,%lo(0x7fffffff),%o0
	ba	4f
	nop
3:
	srl	%o0,20,%o0
	sub	%o0,0x3ff,%o0
4:
	.end

	.inline	rint,1
	fzero	%f4
	fnegd	%f4,%f8
	fabsd	%f0,%f6
	sethi	%hi(0x43300000),%o2
	sllx	%o2,32,%o2
	stx	%o2,[%sp+0x87f]
	ldd	[%sp+0x87f],%f2
	fcmpd	%fcc0,%f6,%f2
	fmovduge %fcc0,%f4,%f2
	fand	%f0,%f8,%f8
	for	%f2,%f8,%f2
	faddd	%f0,%f2,%f0
	fsubd	%f0,%f2,%f0
	fabsd	%f0,%f0
	for	%f0,%f8,%f0
	.end

	.inline	rintf,1
	fzeros	%f4
	fnegs	%f4,%f8
	fabss	%f1,%f6
	sethi	%hi(0x4b000000),%o2
	st	%o2,[%sp+0x87f]
	ld	[%sp+0x87f],%f2
	fcmps	%fcc0,%f6,%f2
	fmovsuge %fcc0,%f4,%f2
	fands	%f1,%f8,%f8
	fors	%f2,%f8,%f2
	fadds	%f1,%f2,%f0
	fsubs	%f0,%f2,%f0
	fabss	%f0,%f0
	fors	%f0,%f8,%f0
	.end

	.inline	min_subnormal,1
	or	%g0,1,%o0
	stx	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	.end

	.inline	min_subnormalf,1
	or	%g0,1,%o0
	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%f0
	.end

	.inline	max_subnormal,1
	xnor	%g0,%g0,%o0
	srlx	%o0,12,%o0
	stx	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	.end

	.inline	max_subnormalf,1
	xnor	%g0,%g0,%o0
	srl	%o0,9,%o0
	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%f0
	.end

	.inline	min_normal,1
	sethi	%hi(0x00100000),%o0
	sllx	%o0,32,%o0
        stx	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	.end

	.inline	min_normalf,1
	sethi	%hi(0x00800000),%o0
	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%f0
	.end

	.inline	max_normal,1
	sethi	%hi(0x80100000),%o1
	sllx	%o1,32,%o1
	xnor	%g0,%g0,%o0
	andn	%o0,%o1,%o0
	stx	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	.end

	.inline	max_normalf,1
	sethi	%hi(0x7f7ffc00),%o0
	or	%o0,0x3ff,%o0
	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%f0
	.end

	.inline	__infinity,1
	sethi	%hi(0x7ff00000),%o0
	sllx	%o0,32,%o0
	stx	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	.end

	.inline	infinity,1
	sethi	%hi(0x7ff00000),%o0
	sllx	%o0,32,%o0
	stx	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	.end

	.inline	infinityf,1
	sethi	%hi(0x7f800000),%o0
	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%f0
	.end

	.inline	signaling_nan,1
	sethi	%hi(0x7ff00000),%o0
	sllx	%o0,32,%o0
	or	%o0,0x1,%o0
	stx	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	.end

	.inline	signaling_nanf,1
	sethi	%hi(0x7f800000),%o0
	or	%o0,1,%o0
	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%f0
	.end

	.inline	quiet_nan,1
	xnor	%g0,%g0,%o0
	srlx	%o0,1,%o0
	stx	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	.end

	.inline	quiet_nanf,1
	xnor	%g0,%g0,%o0
	srl	%o0,1,%o0
	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%f0
	.end

	.inline	__swapEX,1
	and	%o0,0x1f,%o1
	sll	%o1,5,%o1
	.volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	andn	%o0,0x3e0,%o2
	or	%o1,%o2,%o1
	st	%o1,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr
	srl	%o0,5,%o0
	and	%o0,0x1f,%o0
	.nonvolatile
	.end

	.inline	_QgetRD,0
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	srl	%o0,30,%o0
	.end

	.inline	_QgetRP,0
	or	%g0,%g0,%o0
	.end

	.inline	__swapRD,1
	and	%o0,0x3,%o0
	sll	%o0,30,%o1
	.volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	sethi	%hi(0xc0000000),%o4
	andn	%o0,%o4,%o2
	or	%o1,%o2,%o1
	st	%o1,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr
	srl	%o0,30,%o0
	and	%o0,0x3,%o0
	.nonvolatile
	.end

!
! On the SPARC, __swapRP is a no-op; always return 0 for backward compatibility
!
	.inline	__swapRP,1
	or	%g0,%g0,%o0
	.end

	.inline	__swapTE,1
	and	%o0,0x1f,%o0
	sll	%o0,23,%o1
	.volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	sethi	%hi(0x0f800000),%o4
	andn	%o0,%o4,%o2
	or	%o1,%o2,%o1
	st	%o1,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr
	srl	%o0,23,%o0
	and	%o0,0x1f,%o0
	.nonvolatile
	.end

	.inline	fp_class,1
	fabsd	%f0,%f0
	std	%f0,[%sp+0x87f]
	ldx	[%sp+0x87f],%o0
	orcc	%g0,%o0,%g0
	be,pn	%xcc,2f
	nop
	sethi	%hi(0x7ff00000),%o1
	sllx	%o1,32,%o1
	andcc	%o0,%o1,%g0
	bne,pt	%xcc,1f
	nop
	or	%g0,1,%o0
	ba	2f
	nop
1:
	subcc	%o0,%o1,%g0
	bge,pn	%xcc,1f
	nop
	or	%g0,2,%o0
	ba	2f
	nop
1:
	andncc	%o0,%o1,%o0
	bne,pn	%xcc,1f
	nop
	or	%g0,3,%o0
	ba	2f
	nop
1:
	sethi	%hi(0x00080000),%o1
	sllx	%o1,32,%o1
	andcc	%o0,%o1,%g0
	or	%g0,4,%o0
	bne,pt	%xcc,2f
	nop
	or	%g0,5,%o0
2:
	.end

	.inline	fp_classf,1
	fabss	%f1,%f1
	st	%f1,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	orcc	%g0,%o0,%g0
	be,pn	%icc,2f
	nop
1:
	sethi	%hi(0x7f800000),%o1
	andcc	%o0,%o1,%g0
	bne,pt	%icc,1f
	nop
	or	%g0,1,%o0
	ba	2f
	nop
1:
	subcc	%o0,%o1,%g0
	bge,pn	%icc,1f
	nop
	or	%g0,2,%o0
	ba	2f
	nop
1:
	bg,pn	%icc,1f
	nop
	or	%g0,3,%o0
	ba	2f
	nop
1:
	sethi	%hi(0x00400000),%o1
	andcc	%o0,%o1,%g0
	or	%g0,4,%o0
	bne,pt	%icc,2f
	nop
	or	%g0,5,%o0
2:
	.end

	.inline	copysign,2
	fabsd	%f0,%f0
	st	%f0,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	st	%f2,[%sp+0x887]
	ld	[%sp+0x887],%o1
	srl	%o1,31,%o1
	sll	%o1,31,%o1
	or	%o0,%o1,%o0
	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%f0
	.end

	.inline	copysignf,2
	fabss	%f1,%f1
	st	%f1,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	st	%f3,[%sp+0x887]
	ld	[%sp+0x887],%o1
	srl	%o1,31,%o1
	sll	%o1,31,%o1
	or	%o0,%o1,%o0
	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%f0
	.end

	.inline	finite,1
	fabsd	%f0,%f0
	st	%f0,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	sethi	%hi(0x7ff00000),%o1
	sub	%o0,%o1,%o0
	srl	%o0,31,%o0
	.end

	.inline	finitef,1
	fabss	%f1,%f1
	st	%f1,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	sethi	%hi(0x7f800000),%o1
	sub	%o0,%o1,%o0
	srl	%o0,31,%o0
	.end

	.inline	signbit,1
	st	%f0,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	srl	%o0,31,%o0
	.end

	.inline	signbitf,1
	st	%f1,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	srl	%o0,31,%o0
	.end

	.inline	isinf,1
	fabsd	%f0,%f0
	std	%f0,[%sp+0x87f]
	ldx	[%sp+0x87f],%o0
	sethi	%hi(0x7ff00000),%o1
	sllx	%o1,32,%o1
	sub	%o0,%o1,%o0
	sub	%g0,%o0,%o1
	or	%o0,%o1,%o0
	xnor	%o0,%g0,%o0
	srlx	%o0,63,%o0
	.end

	.inline	isinff,1
	fabss	%f1,%f1
	st	%f1,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	sethi	%hi(0x7f800000),%o1
	sub	%o0,%o1,%o0
	sub	%g0,%o0,%o1
	or	%o0,%o1,%o0
	xnor	%o0,%g0,%o0
	srl	%o0,31,%o0
	.end

	.inline	isnan,1
	std	%f0,[%sp+0x87f]
	ldx	[%sp+0x87f],%o0
	sllx	%o0,1,%o0
	srlx	%o0,1,%o0
	sethi	%hi(0x7ff00000),%o1
	sllx	%o1,32,%o1
	sub	%o1,%o0,%o0
	srlx	%o0,63,%o0
	.end

	.inline	isnanf,1
	st	%f1,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	sethi	%hi(0x80000000),%o2
	andn	%o0,%o2,%o0
	sethi	%hi(0x7f800000),%o1
	sub	%o1,%o0,%o0
	srl	%o0,31,%o0
	.end

	.inline	isnormal,1
	fabsd	%f0,%f0
	st	%f0,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	sethi	%hi(0x7ff00000),%o1
	sub	%o0,%o1,%o2
	sethi	%hi(0x00100000),%o1
	sub	%o0,%o1,%o1
	andn	%o2,%o1,%o0
	srl	%o0,31,%o0
	.end

	.inline	isnormalf,1
	fabss	%f1,%f1
	st	%f1,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	sethi	%hi(0x7f800000),%o1
	sub	%o0,%o1,%o2
	sethi	%hi(0x00800000),%o1
	sub	%o0,%o1,%o1
	andn	%o2,%o1,%o0
	srl	%o0,31,%o0
	.end

	.inline	issubnormal,1
	fabsd	%f0,%f0
	std	%f0,[%sp+0x87f]
	ldx	[%sp+0x87f],%o0
	sethi	%hi(0x00100000),%o1
	sllx	%o1,32,%o1
	sub	%o0,%o1,%o1
	sub	%g0,%o0,%o2
	or	%o0,%o2,%o0
	and	%o0,%o1,%o0
	srlx	%o0,63,%o0
	.end

	.inline	issubnormalf,1
	fabss	%f1,%f1
	st	%f1,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	sethi	%hi(0x00800000),%o1
	sub	%o0,%o1,%o1
	sub	%g0,%o0,%o2
	or	%o0,%o2,%o0
	and	%o0,%o1,%o0
	srl	%o0,31,%o0
	.end

	.inline	iszero,1
	fabsd	%f0,%f0
	std	%f0,[%sp+0x87f]
	ldx	[%sp+0x87f],%o0
	sub	%g0,%o0,%o1
	or	%o0,%o1,%o0
	xnor	%o0,%g0,%o0
	srlx	%o0,63,%o0
	.end

	.inline	iszerof,1
	fabss	%f1,%f1
	st	%f1,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	sub	%g0,%o0,%o1
	or	%o0,%o1,%o0
	xnor	%o0,%g0,%o0
	srl	%o0,31,%o0
	.end

	.inline	abs,1
	sra	%o0,31,%o1
	xor	%o0,%o1,%o0
	sub	%o0,%o1,%o0
	sra	%o0,0,%o0
	.end

	.inline	fabs,1
	fabsd	%f0,%f0
	.end

	.inline	fabsf,1
	fabss	%f1,%f0
	.end

!
!	__nintf - f77 NINT(REAL*4)
!
	.inline	__nintf,1
	st	%f1,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	srl	%o0,30-7,%g1
	sethi	%hi(0x7fffff),%o2
	and	%g1,0xff,%g1
	or	%o2,%lo(0x7fffff),%o2
	sethi	%hi(1<<22),%o4
	subcc	%g1,127+31,%g0
	and	%o0,%o2,%o3
	bl	1f
	nop
	sethi	%hi(0xcf000000),%o2
	sethi	%hi(0x80000000),%g1
	subcc	%o0,%o2,%g0
	or	%g1,%g0,%o0
	be	0f
	nop
	fstoi	%f1,%f0
	st	%f0,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
0:
	sra	%o0,0,%o0
	ba	9f
	nop
1:
	add	%o4,%o4,%o5
	or	%o3,%o5,%o3
	sra	%o0,31-0,%o2
	subcc	%g1,127,%g1
	srl	%o4,%g1,%o4
	bge	1f
	nop
	subcc	%g1,-1,%g0
	or	%g0,0,%o0
	bne	2f
	nop
	or	%g0,1,%o0
	ba	2f
	nop
1:
	add	%o3,%o4,%o3
	or	%g0,23,%o0
	subcc	%o0,%g1,%o0
	bl	1f
	nop
	srl	%o3,%o0,%o0
	ba	2f
	nop
1:
	sub	%g0,%o0,%o0
	sll	%o3,%o0,%o0
2:
	xor	%o0,%o2,%o0
	sra	%o0,0,%o0
	and	%o2,1,%o2
	add	%o0,%o2,%o0
9:
	.end

!
!	__i_dnnt - f77 NINT(REAL*8)
!
	.inline	__i_dnnt,1
	ldx	[%o0],%o0
	srlx	%o0,63-11,%g1
	or	%g0,1,%o2
	stx	%o0,[%sp+0x87f]
	sllx	%o2,52-1,%o4
	and	%g1,0x7ff,%g1
	sllx	%o2,63-0,%o2
	subcc	%g1,1023+32,%g0
	bl	0f
	nop
	ldd	[%sp+0x87f],%f0
	ba	8f
	nop
0:
	add	%o4,%o4,%o5
	srax	%o2,63-52,%o2
	sub	%g1,1023+30,%o1
	xnor	%o2,%g0,%o2
	and	%o0,%o2,%o3
	or	%o3,%o5,%o3
	srax	%o0,63-0,%o2
	subcc	%g1,1023,%g1
	bge	1f
	nop
	subcc	%g1,-1,%g0
	or	%g0,0,%o0
	bne	2f
	nop
	or	%g0,1,%o0
	ba	2f
	nop
1:
	srlx	%o4,%g1,%o4
	add	%o3,%o4,%o3
	or	%g0,52,%o0
	sub	%o0,%g1,%o0
	srlx	%o3,%o0,%o0
2:
	xor	%o0,%o2,%o0
	sub	%o0,%o2,%o0
	brlz,pt	%o1,9f
	nop
	stx	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	fxtod	%f0,%f0
8:
	fdtoi	%f0,%f0
	st	%f0,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	sra	%o0,0,%o0
9:
	.end

	.inline	__il_dnnt,1
	ldx	[%o0],%o0
	srlx	%o0,63-11,%g1
	or	%g0,1,%o2
	sllx	%o2,52-1,%o4
	and	%g1,0x7ff,%g1
	sllx	%o2,63-0,%o2
	subcc	%g1,1023+63,%g0
	bl	0f
	nop
	stx	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	fdtox	%f0,%f0
	std	%f0,[%sp+0x87f]
	ldx	[%sp+0x87f],%o0
	ba	9f
	nop
0:
	add	%o4,%o4,%o5
	srax	%o2,63-52,%o2
	sub	%g1,1023+52,%o1
	xnor	%o2,%g0,%o2
	and	%o0,%o2,%o3
	or	%o3,%o5,%o3
	srax	%o0,63-0,%o2
	subcc	%g1,1023,%g1
	bge	1f
	nop
	subcc	%g1,-1,%g0
	or	%g0,0,%o0
	bne	2f
	nop
	or	%g0,1,%o0
	ba	2f
	nop
1:
	brlz,pt	%o1,3f
	nop
	sub	%g1,52,%o0
	sllx	%o3,%o0,%o0
	ba	2f
	nop
3:
	srlx	%o4,%g1,%o4
	add	%o3,%o4,%o3
	or	%g0,52,%o0
	sub	%o0,%g1,%o0
	srlx	%o3,%o0,%o0
2:
	xor	%o0,%o2,%o0
	sub	%o0,%o2,%o0
9:
	.end

	.inline	__aintf,1
	fzeros	%f4
	fnegs	%f4,%f8
	fabss	%f1,%f6
	sethi	%hi(0x4b000000),%o2
	st	%o2,[%sp+0x87f]
	ld	[%sp+0x87f],%f2
	fcmps	%fcc0,%f6,%f2
	fmovsuge %fcc0,%f4,%f6
	fstoi	%f6,%f6
	fitos	%f6,%f6
	fadds	%f1,%f4,%f2
	fmovsuge %fcc0,%f2,%f6
	fands	%f1,%f8,%f0
	fors	%f0,%f6,%f0
	.end

	.inline	__aint,1
	fzero	%f4
	fnegd	%f4,%f8
	fabsd	%f0,%f6
	sethi	%hi(0x43300000),%o2
	sllx	%o2,32,%o2
	stx	%o2,[%sp+0x87f]
	ldd	[%sp+0x87f],%f2
	fcmpd	%fcc0,%f6,%f2
	fmovduge %fcc0,%f4,%f6
	fdtox	%f6,%f6
	fxtod	%f6,%f6
	faddd	%f0,%f4,%f2
	fmovduge %fcc0,%f2,%f6
	fand	%f0,%f8,%f0
	for	%f0,%f6,%f0
	.end

	.inline	__anintf,1
	st	%f1,[%sp+0x87f]
	ld	[%sp+0x87f],%o0
	or	%g0,1,%o1
	srl	%o0,23,%g1
	and	%g1,0xff,%g1
	sub	%g0,%g1,%g1
	add	%g1,0x95,%g1
	subcc	%g1,23,%g0
	sll	%o1,%g1,%o1
	sub	%o1,1,%o2
	bcs	1f
	nop
	be	2f
	nop
	bl	3f
	nop
	sethi	%hi(0x80000000),%o1
	and	%o0,%o1,%o0
	ba	3f
	nop
1:
	and	%o0,%o1,%o1
2:
	add	%o0,%o1,%o0
	andn	%o0,%o2,%o0
3:
	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%f0
	.end

	.inline	__anint,1
	std	%f0,[%sp+0x87f]
	ldx	[%sp+0x87f],%o0
	or	%g0,1,%o1
	srlx	%o0,52,%g1
	and	%g1,0x7ff,%g1
	sub	%g0,%g1,%g1
	add	%g1,0x432,%g1
	subcc	%g1,52,%g0
	sllx	%o1,%g1,%o1
	sub	%o1,1,%o2
	bcs,pt	%icc,1f
	nop
	be,pt	%icc,2f
	nop
	bl,pt	%icc,3f
	nop
	srlx	%o0,63,%o0
	sllx	%o0,63,%o0
	ba	3f
	nop
1:
	and	%o0,%o1,%o1
2:
	add	%o0,%o1,%o0
	andn	%o0,%o2,%o0
3:
	stx	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	.end

	.inline	__r_dim,2
	fzeros	%f4
	ld	[%o0],%f0
	ld	[%o1],%f2
	fcmps	%fcc0,%f0,%f2
	fmovsule %fcc0,%f4,%f2
	fsubs	%f0,%f2,%f0
	fmovsule %fcc0,%f4,%f0
	.end

	.inline	__d_dim,2
	fzero	%f4
	ld	[%o0],%f0
	ld	[%o0+4],%f1
	ld	[%o1],%f2
	ld	[%o1+4],%f3
	fcmpd	%fcc0,%f0,%f2
	fmovdule %fcc0,%f4,%f2
	fsubd	%f0,%f2,%f0
	fmovdule %fcc0,%f4,%f0
	.end

	.inline	__f95_signf,2
	fzeros	%f2
	fnegs	%f2,%f2
	ld	[%o0],%f0
	ld	[%o1],%f1
	fabss	%f0,%f0
	fands	%f1,%f2,%f1
	fors	%f0,%f1,%f0
	.end

	.inline	__f95_sign,2
	fzero	%f4
	fnegd	%f4,%f4
	ld	[%o0],%f0
	ld	[%o0+4],%f1
	ld	[%o1],%f2
	ld	[%o1+4],%f3
	fabsd	%f0,%f0
	fand	%f2,%f4,%f2
	for	%f0,%f2,%f0
	.end

	.inline	__r_sign,2
	ld	[%o0],%f0
	ld	[%o1],%o1
	fabss	%f0,%f0
	fnegs	%f0,%f1
	sub	%o1,1,%o0
	and	%o1,%o0,%o1
	sra	%o1,0,%o1
	fmovrslz %o1,%f1,%f0
	.end

	.inline	__d_sign,2
	ldd	[%o0],%f0
	ldx	[%o1],%o1
	fabsd	%f0,%f0
	fnegd	%f0,%f2
	sub	%o1,1,%o0
	and	%o1,%o0,%o1
	fmovrdlz %o1,%f2,%f0
	.end

!
! complex __Fc_div_f(complex a, complex b);
!
	.inline	__Fc_div_f,0
	fzeros	%f4
	fcmps	%fcc0,%f3,%f4
	fbne,pn	%fcc0,1f
	nop
	fdivs	%f0,%f2,%f0
	fdivs	%f1,%f2,%f1
	ba	2f
	nop
1:
	sethi	%hi(0x3ff00000),%o0
	sllx	%o0,32,%o0
	stx	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f16
	fsmuld	%f2,%f2,%f4
	fsmuld	%f3,%f3,%f6
	fsmuld	%f1,%f3,%f8
	fsmuld	%f0,%f2,%f10
	faddd	%f6,%f4,%f6
	fdivd	%f16,%f6,%f6
	faddd	%f10,%f8,%f10
	fsmuld	%f1,%f2,%f12
	fmuld	%f10,%f6,%f10
	fsmuld	%f0,%f3,%f14
	fsubd	%f12,%f14,%f14
	fmuld	%f14,%f6,%f6
	fdtos	%f10,%f0
	fdtos	%f6,%f1
2:
	.end

!
!	.asciz	"@(#)libsunimath.m4 1.7 02/08/13 SMI"
!
!	Copyright 08/13/02 Sun Microsystems, Inc.  All Rights Reserved
!
	! save fsr and set rounding mode only
	.inline	__libsunimath_swap_RDTE,1
	and	%o0,0x3,%o0
	sll	%o0,30,%o1		! input to RD bit location
	.volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o0		! o0 = fsr
	st	%o1,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr
	.nonvolatile
	.end

	! save fsr and set rounding mode only
	.inline	__libsunimath_swap_RDTE_RN,0
!	set	0x00000000,%o1		! nearest rounding mode RN 0x0
	.volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o0		! o0 = fsr
	st	%g0,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr
	.nonvolatile
	.end

	! save fsr and set rounding mode only
	.inline	__libsunimath_swap_RDTE_RZ,0
	set	0x40000000,%o1		! tozero rounding mode RZ 0x1
	.volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o0		! o0 = fsr
	st	%o1,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr
	.nonvolatile
	.end

	! save fsr and set rounding mode only
	.inline	__libsunimath_swap_RDTE_RP,0
	set	0x80000000,%o1		! positive rounding mode RP 0x2
	.volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o0		! o0 = fsr
	st	%o1,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr
	.nonvolatile
	.end

	! save fsr and set rounding mode only
	.inline	__libsunimath_swap_RDTE_RM,0
	set	0xc0000000,%o1		! negative rounding mode RM 0x3
	.volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o0		! o0 = fsr
	st	%o1,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr
	.nonvolatile
	.end

	! reset fsr from __libsunimath_swap_RDTE()
	.inline	__libsunimath_reset_RDTE,1
	st	%o0,[%sp+0x87f]
	.volatile
	ld	[%sp+0x87f],%fsr	! o0 = fsr
	.nonvolatile
	.end


	.inline	__libsunimath_set_siam_RD_RN,0
	siam	0x4			! force gsr.IM + round-to-nearest-even
	.end

	.inline	__libsunimath_set_siam_RD_RZ,0
	siam	0x5			! force gsr.IM + round-to-zero-even
	.end

	.inline	__libsunimath_set_siam_RD_RP,0
	siam	0x6			! force gsr.IM + round-to-positive-even
	.end

	.inline	__libsunimath_set_siam_RD_RM,0
	siam	0x7			! force gsr.IM + round-to-negative-even
	.end

	.inline	__libsunimath_reset_siam_RD,0
	siam	0x0			! turn off gsr.IM
	.end

	.inline	__libsunimath_getfsr,1
	st	%fsr,[%o0]
	.end

	.inline	__libsunimath_setfsr,1
	ld	[%o0],%fsr
	.end

! return 1 if lb > ub or unordered, 0 otherwise
	.inline __libsunimath_check,1
	ldd	[%o0],%f0
	ldd	[%o0+8],%f2
	fcmpd	%f0,%f2
	mov	0,%o0
	fble	1f
	nop
	mov	1,%o0	! lb > ub or unordered
1:
	.end

! libm.il have this already
	.inline	fabs,2
	sll	%o0,1,%o0
	srl	%o0,1,%o0
	std	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	.end

	.inline	sqrt,2
	std	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	fsqrtd	%f0,%f0
	.end

        .inline __libsunimath_swapRD,1
        and     %o0,0x3,%o0
        sll     %o0,30,%o1              !  input to RD bit location
        st      %fsr,[%sp+0x87f]
        ld      [%sp+0x87f],%o0         ! o0 = fsr
        set     0xc0000000,%o4          ! mask of rounding direction bits
        andn    %o0,%o4,%o2
        or      %o1,%o2,%o1             ! o1 = new fsr
        st      %o1,[%sp+0x87f]
        ld      [%sp+0x87f],%fsr
        srl     %o0,30,%o0
        and     %o0,0x3,%o0
        .end

	.inline __ri_inf_,1
!	return (xp->l);
	ld	[%o0],%f0
	.end

	.inline __di_inf_,1
!	return (xp->l);
	ldd	[%o0],%f0
	.end

	.inline __ri_sup_,1
!	return (xp->u);
	ld	[%o0+4],%f0
	.end

	.inline __di_sup_,1
!	return (xp->u);
	ldd	[%o0+8],%f0
	.end

	.inline __ri_isempty_,1
!	float a;
!	return ((a = xp->l) != a && (a = xp->u) != a);
	ld	[%o0+0x0],%f0
	fcmps	%f0,%f0
	nop
	fbe,pt	%fcc0,	1f
	nop
	ld	[%o0+0x4],%f0
	fcmps	%f0,%f0
	nop
	fbe,pt	%fcc0,	1f
	nop
	mov	1,%o0
	ba	2f
	nop
1:
	mov	0,%o0
2:
	.end

	.inline __di_isempty_,1
!	double a;
!	return ((a = xp->l) != a && (a = xp->u) != a);
	ldd	[%o0+0x0],%f0
	fcmpd	%f0,%f0
	nop
	fbe,pt	%fcc0,	1f
	nop
	ldd	[%o0+0x8],%f0
	fcmpd	%f0,%f0
	nop
	fbe,pt	%fcc0,	1f
	nop
	mov	1,%o0
	ba	2f
	nop
1:
	mov	0,%o0
2:
	.end

	.inline _asm_get_fp, 8
	ta	0x03
	st	%fp, [%o0]
	st	%sp, [%o1]
	.end


	.inline __ri_add_, 3

!	void
!	__ri_add_(r_interval * zp, r_interval * xp, r_interval * yp)
!
!	zp->l = -(-(xp->l) - (yp->l));

	ld	[%o1+0x0],%f0
	ld	[%o1+0x4],%f1

	ld	[%o2+0x0],%f2
	ld	[%o2+0x4],%f3

!	save rounding

	! Sri: .volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o5		! o5 = fsr
	set	0xc0000000,%o4		! flush rounding bits
	andn	%o5,%o4,%o2		! flush rounding bits
	set	0x80000000,%o1		! load FP_RP == 2 sll 30 to o1
	or	%o1,%o2,%o1		! o1 = new fsr | FP_RP
	st	%o1,[%sp+0x87f]		! fsr = o1
	ld	[%sp+0x87f],%fsr
	! Sri: .nonvolatile


	fnegs	%f0,%f0

	fsubs	%f0,%f2,%f2
	fnegs	%f2,%f2
	st	%f2,[%o0+0x0]

!	zp->u = (xp->u) + (yp->u);

	fadds	%f1,%f3,%f3
	st	%f3,[%o0+0x4]

!	restore rounding

	! Sri: .volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o1		! o1 = fsr
	set	0xc0000000,%o4		! flush rounding bits
	andn	%o1,%o4,%o1		! flush rounding bits
	and	%o5,%o4,%o5		! flush not rounding bits
	or	%o1,%o5,%o1		! o1 = new old fsr
	st	%o1,[%sp+0x87f]		! fsr = o1
	ld	[%sp+0x87f],%fsr
	! Sri: .nonvolatile

	.end


	.inline __di_add_, 3

!	void
!	__di_add_(d_interval * zp, d_interval * xp, d_interval * yp)
!
!	zp->l = -(-(xp->l) - (yp->l));

	ldd	[%o1+0x0],%f0
!	ld	[%o1+0x4],%f1

	ldd	[%o1+0x8],%f2
!	ld	[%o1+0xc],%f3

	ldd	[%o2+0x0],%f4
!	ld	[%o2+0x4],%f5

	ldd	[%o2+0x8],%f6
!	ld	[%o2+0xc],%f7

!	save rounding

	! Sri: .volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o5		! o5 = fsr
	set	0xc0000000,%o4		! flush rounding bits
	andn	%o5,%o4,%o2		! flush rounding bits
	set	0x80000000,%o1		! load FP_RP == 2 sll 30 to o1
	or	%o1,%o2,%o1		! o1 = new fsr | FP_RP
	st	%o1,[%sp+0x87f]		! fsr = o1
	ld	[%sp+0x87f],%fsr
	! Sri: .nonvolatile


	fnegs	%f0,%f0

	fsubd	%f0,%f4,%f4
	fnegs	%f4,%f4
	std	%f4,[%o0+0x0]
!	st	%f5,[%o0+0x4]

!	zp->u = (xp->u) + (yp->u);

	faddd	%f2,%f6,%f6
	std	%f6,[%o0+0x8]
!	st	%f7,[%o0+0xc]

!	restore rounding

	! Sri: .volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o1		! o1 = fsr
	set	0xc0000000,%o4		! flush rounding bits
	andn	%o1,%o4,%o1		! flush rounding bits
	and	%o5,%o4,%o5		! flush not rounding bits
	or	%o1,%o5,%o1		! o1 = new old fsr
	st	%o1,[%sp+0x87f]		! fsr = o1
	ld	[%sp+0x87f],%fsr
	! Sri: .nonvolatile

	.end


	.inline __ri_sub_, 3

!	void
!	__ri_sub_(r_interval * zp, r_interval * xp, r_interval * yp)
!
!	zp->l = -(-(xp->l) + (yp->u));

	ld	[%o1+0x0],%f0
	ld	[%o1+0x4],%f1

	ld	[%o2+0x0],%f2
	ld	[%o2+0x4],%f3

!	save rounding

	! Sri: .volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o5		! o5 = fsr
	set	0xc0000000,%o4		! flush rounding bits
	andn	%o5,%o4,%o2		! flush rounding bits
	set	0x80000000,%o1		! load FP_RP == 2 sll 30 to o1
	or	%o1,%o2,%o1		! o1 = new fsr | FP_RP
	st	%o1,[%sp+0x87f]		! fsr = o1
	ld	[%sp+0x87f],%fsr
	! Sri: .nonvolatile


	fnegs	%f0,%f0

	fadds	%f0,%f3,%f3
	fnegs	%f3,%f3
	st	%f3,[%o0+0x0]

!	zp->u = (xp->u) - (yp->l);

	fsubs	%f1,%f2,%f2
	st	%f2,[%o0+0x4]

!	restore rounding

	! Sri: .volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o1		! o1 = fsr
	set	0xc0000000,%o4		! flush rounding bits
	andn	%o1,%o4,%o1		! flush rounding bits
	and	%o5,%o4,%o5		! flush not rounding bits
	or	%o1,%o5,%o1		! o1 = new old fsr
	st	%o1,[%sp+0x87f]		! fsr = o1
	ld	[%sp+0x87f],%fsr
	! Sri: .nonvolatile

	.end


	.inline __di_sub_, 3

!	void
!	__di_sub_(d_interval * zp, d_interval * xp, d_interval * yp)
!
!	zp->l = -(-(xp->l) + (yp->u));

	ldd	[%o1+0x0],%f0
!	ld	[%o1+0x4],%f1

	ldd	[%o1+0x8],%f2
!	ld	[%o1+0xc],%f3

	ldd	[%o2+0x0],%f4
!	ld	[%o2+0x4],%f5

	ldd	[%o2+0x8],%f6
!	ld	[%o2+0xc],%f7


!	save rounding

	! Sri: .volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o5		! o5 = fsr
	set	0xc0000000,%o4		! flush rounding bits
	andn	%o5,%o4,%o2		! flush rounding bits
	set	0x80000000,%o1		! load FP_RP == 2 sll 30 to o1
	or	%o1,%o2,%o1		! o1 = new fsr | FP_RP
	st	%o1,[%sp+0x87f]		! fsr = o1
	ld	[%sp+0x87f],%fsr
	! Sri: .nonvolatile


	fnegs	%f0,%f0

	faddd	%f0,%f6,%f6
	fnegs	%f6,%f6
	std	%f6,[%o0+0x0]
!	st	%f7,[%o0+0x4]

!	zp->u = (xp->u) - (yp->l);

	fsubd	%f2,%f4,%f4
	std	%f4,[%o0+0x8]
!	st	%f5,[%o0+0xc]

!	restore rounding

	! Sri: .volatile
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o1		! o1 = fsr
	set	0xc0000000,%o4		! flush rounding bits
	andn	%o1,%o4,%o1		! flush rounding bits
	and	%o5,%o4,%o5		! flush not rounding bits
	or	%o1,%o5,%o1		! o1 = new old fsr
	st	%o1,[%sp+0x87f]		! fsr = o1
	ld	[%sp+0x87f],%fsr
	! Sri: .nonvolatile

	.end


	.inline __ri_wid_, 1

!	float
!	__ri_wid_(r_interval * xp)

	ld	[%o0+0x0],%f0
	ld	[%o0+0x4],%f1

	siam	0x6			! force gsr.IM + round-to-positive-even
	fsubs	%f1,%f0,%f0
	siam	0x0			! turn off gsr.IM

	.end

	.inline __di_wid_, 1

!	double
!	__di_wid_(d_interval * xp)

	ldd	[%o0+0x0],%f0
	ldd	[%o0+0x8],%f2

	siam	0x6			! force gsr.IM + round-to-positive-even
	fsubd	%f2,%f0,%f0
	siam	0x0			! turn off gsr.IM

	.end

	.inline __ri_wid_, 1

!	float
!	__ri_wid_(r_interval * xp)

	ld	[%o0+0x0],%f0
	ld	[%o0+0x4],%f1

!	save fsr, set rounding mode positive

	set	0x80000000,%o1		! positive rounding mode RP 0x2
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o0		! o0 = fsr
	st	%o1,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr

	fsubs	%f1,%f0,%f0

!	restore fsr

	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr	! o0 = fsr

	.end

	.inline __di_wid_, 1

!	double
!	__di_wid_(d_interval * xp)

	ldd	[%o0+0x0],%f0
	ldd	[%o0+0x8],%f2

!	save fsr, set rounding mode positive

	set	0x80000000,%o1		! positive rounding mode RP 0x2
	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o0		! o0 = fsr
	st	%o1,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr

	fsubd	%f2,%f0,%f0

!	restore fsr

	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr	! o0 = fsr

	.end


	.inline __ri_mid_, 1
!	float
!	__ri_mid_(r_interval * xp) {

	ld	[%o0+0],%f0
	ld	[%o0+4],%f1

!	return (xl == xu ? xl : -xl == xu ? 0.0f : 0.5f * xl + 0.5f * xu);
!	note : arithmetic expression computes under nearest rounding mode

	fcmps	%f0,%f1
	nop
	fbe,pt	%fcc0,	1f
	nop

	fnegs	%f0,%f0
	fcmps	%f0,%f1
	nop
	fbne,pt	%fcc0,	2f
	nop

	st	%g0,[%sp+0x87f]
	ld	[%sp+0x87f],%f0
	ba	1f
	nop
2:
	fnegs	%f0,%f0
	set	0x3f000000,%o0
	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%f2
	siam	0x4			! force gsr.IM + round-to-nearest-even
	fmuls	%f0,%f2,%f0
	fmuls	%f1,%f2,%f1
	fadds	%f0,%f1,%f0
	siam	0x0			! turn off gsr.IM
1:
	.end

	.inline __di_mid_, 1
!	double
!	__di_mid_(d_interval * xp) {

	ldd	[%o0+0],%f0
	ldd	[%o0+8],%f2

!	return (xl == xu ? xl : -xl == xu ? 0.0 : 0.5 * xl + 0.5 * xu);
!	note : arithmetic expression computes under nearest rounding mode

	fcmpd	%f0,%f2
	nop
	fbe,pt	%fcc0,	1f
	nop

	fnegs	%f0,%f0
	fcmpd	%f0,%f2
	nop
	fbne,pt	%fcc0,	2f
	nop

	stx	%g0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	ba	1f
	nop
2:
	fnegs	%f0,%f0
	set	0x3fe00000,%o0
	set	0x00000000,%o1
	std	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f4
	siam	0x4			! force gsr.IM + round-to-nearest-even
	fmuld	%f0,%f4,%f0
	fmuld	%f2,%f4,%f2
	faddd	%f0,%f2,%f0
	siam	0x0			! turn off gsr.IM
1:
	.end

	.inline __ri_mid_, 1
!	float
!	__ri_mid_(r_interval * xp) {

	ld	[%o0+0],%f0
	ld	[%o0+4],%f1

!	return (xl == xu ? xl : -xl == xu ? 0.0f : 0.5f * xl + 0.5f * xu);
!	note : arithmetic expression computes under nearest rounding mode,
!		fsr is zero

	fcmps	%f0,%f1
	nop
	fbe,pt	%fcc0,	1f
	nop

	fnegs	%f0,%f0
	fcmps	%f0,%f1
	nop
	fbne,pt	%fcc0,	2f
	nop

	st	%g0,[%sp+0x87f]
	ld	[%sp+0x87f],%f0
	ba	1f
	nop
2:
	fnegs	%f0,%f0
	set	0x3f000000,%o0
	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%f2

!	save fsr, set rounding mode nearest

	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o0		! o0 = fsr
	st	%g0,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr

	fmuls	%f0,%f2,%f0
	fmuls	%f1,%f2,%f1
	fadds	%f0,%f1,%f0

!	restore fsr

	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr	! o0 = fsr
1:
	.end

	.inline __di_mid_, 1
!	double
!	__di_mid_(d_interval * xp) {

	ldd	[%o0+0],%f0
	ldd	[%o0+8],%f2

!	return (xl == xu ? xl : -xl == xu ? 0.0 : 0.5 * xl + 0.5 * xu);
!	note : arithmetic expression computes under nearest rounding mode,
!		fsr is zero

	fcmpd	%f0,%f2
	nop
	fbe,pt	%fcc0,	1f
	nop

	fnegs	%f0,%f0
	fcmpd	%f0,%f2
	nop
	fbne,pt	%fcc0,	2f
	nop

	stx	%g0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f0
	ba	1f
	nop
2:
	fnegs	%f0,%f0
	set	0x3fe00000,%o0
	set	0x00000000,%o1
	std	%o0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f4

!	save fsr, set rounding mode nearest

	st	%fsr,[%sp+0x87f]
	ld	[%sp+0x87f],%o0		! o0 = fsr
	st	%g0,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr

	fmuld	%f0,%f4,%f0
	fmuld	%f2,%f4,%f2
	faddd	%f0,%f2,%f0

!	restore fsr

	st	%o0,[%sp+0x87f]
	ld	[%sp+0x87f],%fsr	! o0 = fsr
1:
	.end

	.inline __ri_mig_, 1
!	float
!	__ri_mig_(r_interval * xp) {

	ld	[%o0+0],%f0
	ld	[%o0+4],%f1

!	return (xl <= 0.0f && xu >= 0.0f ? 0.0f : xl < 0.0f ? -xu : xl);
	st	%g0,[%sp+0x87f]
	ld	[%sp+0x87f],%f2
	fcmps	%f0,%f2
	nop
	fbug,pt	%fcc0,	1f
	nop

	fcmps	%f1,%f2
	nop
	fbul,pt	%fcc0,	1f
	nop

	fmovs	%f2,%f0
	ba	2f
	nop
1:
	fcmps	%f0,%f2
	nop
	fbug,pt	%fcc0,	2f
	nop

	fnegs	%f1,%f1
	fmovs	%f1,%f0
2:
	.end

	.inline __di_mig_, 1
!	double
!	__di_mig_(d_interval * xp) {

	ldd	[%o0+0],%f0
	ldd	[%o0+8],%f2

!	return (xl <= 0.0 && xu >= 0.0 ? 0.0 : xl < 0.0 ? -xu : xl);
	stx	%g0,[%sp+0x87f]
	ldd	[%sp+0x87f],%f4
	fcmpd	%f0,%f4
	nop
	fbug,pt	%fcc0,	1f
	nop

	fcmpd	%f2,%f4
	nop
	fbul,pt	%fcc0,	1f
	nop

	fmovd	%f4,%f0
	ba	2f
	nop
1:
	fcmpd	%f0,%f4
	nop
	fbug,pt	%fcc0,	2f
	nop

	fnegs	%f2,%f2
	fmovd	%f2,%f0
2:
	.end

	.inline __ri_mag_, 1
!	float
!	__ri_mag_(r_interval * xp) {

	ld	[%o0+0],%f0
	ld	[%o0+4],%f1

!	xl = fabsf(xp->l);
!	xu = fabsf(xp->u);
!	return (xl >= xu ? xl : xu);

	fabss	%f0,%f0
	fabss	%f1,%f1
	fcmps	%f0,%f1
	fmovsl	%fcc0,%f1,%f0
	.end

	.inline __di_mag_, 1
!	double
!	__di_mag_(d_interval * xp) {

	ldd	[%o0+0],%f0
	ldd	[%o0+8],%f2

!	xl = fabs(xp->l);
!	xu = fabs(xp->u);
!	return (xl >= xu ? xl : xu);

	fabss	%f0,%f0
	fabss	%f2,%f2
	fcmpd	%f0,%f2
	fmovdl	%fcc0,%f2,%f0
	.end
