Patch-ID# 108885-11 Keywords: Starfire hpost Synopsis: SSP 3.3: Modify POST/SSP to support CIC2 asic and new ecache SRAM Date: Dec/17/2002 Install Requirements: See Special Install Instructions Solaris Release: 2.6 7 8 SunOS Release: 5.6 5.7 5.8 Unbundled Product: System Service Processor Unbundled Release: 3.3 Xref: Topic: SSP 3.3: Modify POST/SSP to support CIC2 asic and new ecache SRAM Relevant Architectures: sparc BugId's fixed with this patch: 4267476 4268088 4293712 4310528 4312909 4319605 4320022 4324299 4327649 4355442 4358487 4360376 4362960 4366498 4369154 4369241 4397802 4401066 4402889 4415072 4417673 4423595 4425374 4425375 4433894 4458358 4518294 4614733 Changes incorporated in this version: 4310528 Patches accumulated and obsoleted by this patch: 109919-01 Patches which conflict with this patch: Patches required with this patch: Obsoleted by: Files included with this patch: /opt/SUNWssp/bin/acfg_check /opt/SUNWssp/bin/acfg_update_db /opt/SUNWssp/lib/libxpost.so /opt/SUNWssp/release/Ultra-Enterprise-10000/5/5/1/bin/hpost /opt/SUNWssp/release/Ultra-Enterprise-10000/5/5/1/bin/redx /opt/SUNWssp/release/Ultra-Enterprise-10000/5/5/1/hostobjs/rn.elf /opt/SUNWssp/release/Ultra-Enterprise-10000/5/5/1/hostobjs/stage0.elf /opt/SUNWssp/release/Ultra-Enterprise-10000/5/5/1/hostobjs/stage1.elf /opt/SUNWssp/release/Ultra-Enterprise-10000/5/5/1/hostobjs/stage2.elf /opt/SUNWssp/release/Ultra-Enterprise-10000/5/5/1/hostobjs/stage3.elf /opt/SUNWssp/release/Ultra-Enterprise-10000/5/5/1/hostobjs/stage4.elf /opt/SUNWssp/release/Ultra-Enterprise-10000/5/5/1/hostobjs/stage5.elf /opt/SUNWssp/release/Ultra-Enterprise-10000/5/5/1/hostobjs/stagei.elf /var/opt/SUNWssp/data/Ultra-Enterprise-10000/common/board/sysboard/chip.ids /var/opt/SUNWssp/data/Ultra-Enterprise-10000/common/board/sysboard/rev1/BS1.chips /var/opt/SUNWssp/data/Ultra-Enterprise-10000/common/board/sysboard/rev1/BS2.chips /var/opt/SUNWssp/data/Ultra-Enterprise-10000/common/board/sysboard/rev1/BS3.chips /var/opt/SUNWssp/data/Ultra-Enterprise-10000/common/chip/cic/rev1/cic.chains /var/opt/SUNWssp/data/Ultra-Enterprise-10000/common/chip/cic/rev1/history1.fields /var/opt/SUNWssp/data/Ultra-Enterprise-10000/common/chip/sombra/rev1/bypass.fields /var/opt/SUNWssp/data/Ultra-Enterprise-10000/common/chip/sombra/rev1/id.fields /var/opt/SUNWssp/data/Ultra-Enterprise-10000/common/chip/sombra/rev1/sombra.chains Problem Description: 4310528 Bringup with centerplane configuration shows errors in post test for IOC's (from 108885-10) 4401066 Need to identify mirrored SRAM cpu modules after bringup/DR 4518294 Error message confuses customers and needs to be changed 4614733 Enhancement needed to handle rev0 & rev1 mirrored tag srams (from 108885-09) 4458358 POST ecache TAG test enhancement needed. (from 108885-08) 4415072 "Bogus clk_mode" errors during phase proc1 for Arbstop/Recordstop/Timeout 4417673 hpost phase timeout value incorrect for 64-proc configurations 4423595 Fix ecache parity testing to match Sunfire test patterns 4425374 Enhance "unexpected foreign PIO" and "MC Timeout" messaging 4425375 Improve handling of long user input lines 4433894 autoconfig WARNING for new MSRAM ID needs special change (from 108885-07) 4397802 wfail does not FAIL procs for CIC "Coherent error processor " 4402889 Bringup does not verify that bootproc returned from HPOST is in domain. (from 108885-06) 4268088 Modify POST/SSP to Reflect Processor Speed of 466MHz 4366498 Create new hpost ecache tests for new ecache SRAM. (from 108885-05) 4369241 Backing out autconfig patch can cause SSP to become non-functional (from 108885-04) 4369154 SSP patch 108885-03 has packaging problems. (from 108885-03) 4358487 stop_handler_cic() INTERNAL errors output for wfail of CIC/GAB dump 4362960 POST changes required to support new ecache SRAM (from 108885-02) 4327649 init_attach failure, MCs programmed for same logical board (memory interleaved) (from 108885-01) 4267476 New JTAG CID's required for CPU/BDB/DTAG/CIC 4293712 Hpost fails "Mixed Ecache sizes" even though system has the same size proc/cache 4312909 Improve UPA Fatal Error message 4319605 Modify POST/SSP to support CIC2 asic 4320022 Modify SSP scantool database for CIC2, for autoconfig use (from 109919-01) 4324299 SSP upgrade renders CPUS inaccessible after autoconfig 4355442 autoconfig creates multiple rev subdirectories within rev directories 4360376 autoconfig changes required to support new ecache srams Patch Installation Instructions: -------------------------------- Refer to the Install.info file within the patch for instructions on using the generic 'installpatch' and 'backoutpatch' scripts provided with each patch. Any other special or non-generic installation instructions should be described below. Special Install Instructions: ----------------------------- *** PLEASE SEE THE CURRENT VERSION OF THE SSP3.3 INSTALLATION GUIDE AND RELEASE NOTES *** Installation Issues The information presented in this section is for use by authorized service providers only. ----------- Revision -10 of this patch gives authorized Sun personnel the ability to track processor modules that have mirrored SRAM (MSRAM) ecache. This patch revision contains changes to autoconfig(1M) and hpost(1M), which enable tracking of MSRAM processor modules. Another separate but related patch involves a change to obp(1M) for MSRAM detection. The obp(1M) patch number is: 109661-05 (OBP) If you use OBP patch 109661-05, it is suggested that you also apply hpost patch 108885-10 (revision -10 of this patch) to your SSP, so that the new MSRAM tracking information can be properly handed off from hpost to OBP. However, OBP patch 109661-05 can be applied to an SSP and function normally without the application of hpost patch 108885-10. If you apply the OPB patch but not the hpost patch, the MSRAM tracking information will not be available from hpost for handoff to OBP. ----------- Revision -03 and -01 of this patch affects system boards that contain: - MSRAM processor modules with the following part numbers: 501-5838 501-5866 501-6008 - Revision 2 CIC ASICs Note: If your system boards do not include these specific processor modules and ASICs, you do not need to perform the steps described below. If you are using system boards that contain mirrored SRAM processor modules or Revision 2 CIC ASICs (or both), you must perform the following steps after installing this patch: 1. Run the autoconfig(1M) command on each system board that contains mirrored SRAM processor modules or Revision 2 CIC ASICs. You must run autoconfig(1M) on these system boards before the boards run POST. The POST changes included in this patch require the scan and configuration updates that result from running autoconfig(1M). 2. After running autoconfig(1M) on these system boards, reboot the SSP, which restarts the control board server (CBS). 3. If there is a spare SSP present, install the patch onto the spare SSP, then reboot the spare SSP. 4. Run ssp_backup on the main SSP. The SSP configures the JTAG database to support the mirrored SRAM processor modules. The Scantool database is also updated to support the JTAG history chain in the current libcbs for each system board containing Revision 2 CIC ASICs. From this point forward, you can successfully run the hpost(1M) and bringup(1M) commands on system boards that contain mirrored SRAM processor modules or Revision 2 CIC ASICs. ----------- Revision -01 of this patch: POST and Revision 2 CIC ASICs ----------------------------- When POST encounters a Revision 2 CIC ASIC on a system board, it checks the Scantool database. If autoconfig(1M) was not run for the system board, the new history chain is not supported in the current libcbs for the system board. POST fails the system board and displays failure messages similar to the following: Reading centerplane asics to obtain bus configuration... Bus configuration determined to be 3F. phase cplane_isolate: CP domain cluster mask clear... phase init_reset: Initial system resets... phase jtag_integ: JTAG probe and integrity test... ERR: libcbs:cbs_chain_info:libscan error ERR: xp_get_chain_bits(): sd_chain_info() error FAIL Sysbrd 2: CIC rev 2 JTAG history chain not reflected in scantool database. `autoconfig' must be run for Sysbd 2 A POST failure for a system board with Revision 2 CIC ASICs can occur under the following circumstances: o You install system boards with Revision 2 CIC ASICs and also install this patch, but you do not run the autoconfig command for each system board before those system boards run POST. o The operating system is running, and you perform a dynamic reconfiguration (DR) operation, where a system board with Revision 1 CIC ASICs is detached and a system board with Revision 2 CIC ASICs is attached. In addition, you - Install this patch while the operating system is booted - Do not run autoconfig for system boards with Revision 2 CIC ASICs before those system boards run POST You must run POST if you shut down the domain associated with a system board. If an operating system error occurred, POST is automatically initiated. In either case, running POST without previously running autoconfig on the system boards with Revision 2 CIC ASICs will cause the POST failure described above. o You install this patch while the operating system is booted, but you - Do not run autoconfig for system boards with Revision 2 CIC ASICs - Perform a DR operation where a system board with Revision 1 CIC ASICs is detached and a system board with Revision 2 CIC ASICs is attached The DR operation will fail and POST failure messages will be displayed because autoconfig was not run for the system board before the DR attachment. ------------------------------------------------------------------------ Changes to postrc.4 Command The following new properties for the postrc.4 command are intended for use by Sun Microsystems and authorized service providers only. force_dtag_parity_mode (Level 2) If a Sun Enterprise 10000 system board is populated with Revision 2 CIC ASICs, POST normally configures those CICs for Dtag Error Checking and Correction (ECC) mode, provided that the on-board processors have the minimum external cache (Ecache) size required to support Dtag ECC mode. ECC allows single-bit errors in Dtag SRAM reads to be corrected by the CIC hardware without affecting domain operation. However, single-bit errors in parity mode cause fatal arbstop errors. This property tells POST to always configure CICs in Dtag parity mode, even when ECC mode is possible. no_dtag_ecc_ce_scrub (Level 2) Revision 2 CIC ASICs configured in Dtag ECC mode will correct any single-bit errors that are detected during Dtag SRAM accesses. Normally, the corrected data is also written back to the SRAM. This function, which is called scrubbing, fixes the Correctable Errors (CE) of the Dtag SRAM and eliminates recurring CEs during subsequent Dtag SRAM accesses. This property tells POST to disable the scrubbing function in the CIC ASIC configuration. README -- Last modified date: Tuesday, December 17, 2002